V1621

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Instruction summary

Instruction names	Identification code	Instruction code	Instruction type	function	The default
READ	110	A5A4A3A2A1A0D0D1D2D3	Data manipulation	The RAM
WRITE	101	A5A4A3A2A1A0D0D1D2D3	Data manipulation	The RAM
READ-MODIFY -WRITE	101	A5A4A3A2A1A0D0D1D2D3	Data manipulation	The RAM to read and write operations
SYS DIS	100	0000 0000x	Mode setting	System resonator oscillation stop LCD bias to stop working	is
SYS EN	100	0000 0001x	Mode setting	Vibration system resonator
LCD OFF	100	0000 0010x	Mode setting	LCD bias to stop working	is
LCD ON	100	0000 0011x	Mode setting	LCD bias began to work
TIMER DIS	100	0000 0100x	Mode setting	Benchmark clock output
WDT DIS	100	0000 0101x	Mode setting	WDT overflow mark not output
TIMER EN	100	0000 0110x	Mode setting	Reference clock output
WDT EN	100	0000 0111x	Mode setting	WDT overflow flag allows the output
TONE OFF	100	0000 1000x	Mode setting	Audio output shut down	is
TONE ON	100	0000 1001x	Mode setting	Audio output open
CLR TIMER	100	0000 11xxx	Mode setting	Reference clock reset
CLR WDT	100	0000 111xx	Mode setting	Resets the watchdog timer
XTAL 32K	100	0001 01xxx	Mode setting	The system clock by 32 KHZ crystals
RC 256K	100	0001 10xxx	Mode setting	The system clock oscillator in splicing	is
EXT 256K	100	0001 11xxx	Mode setting	The system clock meet external clock source

Instruction names	Identification code	Instruction code	Instruction type	function	The default
BIAS 1/2	100	0010 abx0x	Mode setting	LCD 1/2 offset option Ab = 00:2 public side Ab = 01:3 public side Ab = when a public side
BIAS 1/3	100	0010 abx1x	Mode setting	LCD 1/3 offset option Ab = 00:2 public side Ab = 01:3 public side Ab = when a public side
TONE 4K	100	010x xxxxx	Mode setting	Audio output frequency of 4 KHZ
TONE 2K	100	011x xxxxx	Mode setting	Audio output frequency is 2 KHZ
IRQB DIS	100	100x 0xxxx	Mode setting	IRQB output is prohibited	is
IRQB EN	100	100x 1xxxx	Mode setting	IRQB output allows
F1	100	101x x000x	Mode setting	Reference clock/WDT clock output 1 hz; WDT overflow mark the time lag for the 4 s
F2	100	101x x001x	Mode setting	For the reference clock/WDT clock output 2 hz; WDT overflow mark lag After the time for 2 s
F4	100	101x x010x	Mode setting	For the reference clock/WDT clock output 4 hz; WDT overflow mark lag After the time of 1 s
F8	100	101x x011x	Mode setting	Reference clock/WDT clock output of 8 hz; WDT overflow mark lag Time for 1/2 after s
F16	100	101x x100x	Mode setting	Reference clock/WDT clock output for 16 hz; WDT overflow mark lag Time for a quarter after s
F32	100	101x x101x	Mode setting	Reference clock/WDT clock output is 32 hz; WDT overflow mark lag After the time for 1/8 SEC
F64	100	101x x110x	Mode setting	Reference clock/WDT clock output for 64 hz; WDT overflow mark lag After the time for 1/16 SEC
F128	100	101x x111x	Mode setting	Reference clock/WDT clock output for 128 hz; WDT overflow mark The time lag for 1/32 SEC	is
TOPT	100	1110 0000x	Mode setting	Test mode
TNORMAL	100	1110 0011x	Mode setting	Normal mode	is

Note:

X: useless; A5 ~ A0: RAM address; Do ~ D3: RAM data; Default: after power on default values.

  After power on V1621 master control chip for the initialization,
because if the electric reset failed, may causeV1621 misoperation.